1. Field of the Invention
This invention relates to an analog-to-digital conversion circuit which converts an analog signal into a digital signal.
2. Description of the Background Art
In recent years, the demands for analog-to-digital conversion circuits (A/D converters) for processing video signals have grown with advance in digital processing techniques for video signals. The high-speed conversion operations are required for the analog-to-digital conversion circuits for processing video signals. For this reason, conventionally, two-step flash (two-step parallel) systems have been widely used.
However, with an increase in the number of converted bits, it has become difficult to obtain sufficient conversion accuracy in the two-step flash systems. Therefore, analog-to-digital conversion circuits having multi-stage pipeline structures have been developed.
FIG. 35 is a block diagram showing the structure of an analog-to-digital conversion circuit having a conventional multi-stage pipeline structure. The analog-to-digital conversion circuit shown in FIG. 35 has a 10-bit four-stage pipeline structure.
In FIG. 35, the analog-to-digital conversion circuit 101 comprises a first-stage circuit 103, a second-stage circuit 104, a third-stage circuit 105, a fourth-stage circuit 106, a plurality of latch circuits 107, and an output circuit 108.
Each of the first (initial)-to third-stage circuits 103 to 105 comprises a sub-A/D converter 109, a sub-D/A (digital-to-analog) converter 110, a subtraction circuit 112, and an operational amplifier 111. The fourth (final)-stage circuit 106 comprises only a sub-A/D converter 109. In the following description, the subtraction circuit 112 and the operational amplifier 111 constitute a differential amplifier circuit 114.
The first-stage circuit 103 has a 4-bit configuration, and each of the second- to fourth-stage circuits has a 2-bit configuration. In each of the first- to third-stage circuits 103 to 105, the respective numbers of bits (bit configurations) of the sub-A/D converter 109 and the D/A converter 110 are set to the same value.
The operations of the analog-to-digital conversion circuit 101 will be then described. Analog-to-digital conversion will be hereinafter abbreviated to A/D conversion.
First, an analog input signal Vin is transferred to the first-stage circuit 103. In the first-stage circuit 103, the sub-A/D converter 109 subjects the analog input signal Vin to A/D conversion. A high order 4-bit digital output D9, D8, D7, D6, which is the result of the A/D conversion by the sub-A/D converter 109, is transferred to the sub-D/A converter 110, and is also transferred to the output circuit 108 through the four latch circuits 107.
The subtraction circuit 112 subtracts the result of the D/A conversion by the sub-D/A converter 110 from the analog input signal Vin. The operational amplifier 111 amplifies an output from the subtraction circuit 112. An output from the operational amplifier 111 is transferred to the second-stage circuit 104.
The second-stage circuit 104 carries out the same operations as those of the first-stage circuit 103 with respect to the output from the operational amplifier 111 in the first-stage circuit 103. The third-stage circuit 105 also carries out the same operations as those of the first-stage circuit 103 with respect to an output from the operational amplifier 111 in the second-stage circuit 104. Accordingly, an intermediate high order 2-bit digital signal D5, D4 is obtained from the second-stage circuit 104, and an intermediate low order two-bit digital signal D3, D2 is obtained from the third-stage circuit 105.
In the fourth-stage circuit 106, the sub-A/D converter 109 subjects an output from the operational amplifier 111 in the third-stage circuit 105 to A/D conversion, such that a low order two-bit digital signal D1, D0 is obtained.
The digital signals D9 to D0 from the first- to fourth-stage circuits 103 to 106 simultaneously reach the output circuit 108 through the respective latch circuits 107. In other words, the latch circuits 107 are provided to synchronize the respective outputs of the digital signals D9 to D0 from the circuits 103 to 106 with each other.
The output circuit 108 outputs a 10-bit digital output value Dout of the analog input signal Vin.
In the analog-to-digital conversion circuit 101, in each of the circuits 103 to 105, the operational amplifier 111 amplifies the difference between the analog input signal Vin or the output from the operational amplifier 111 in the previous stages of circuits 103 or 104 and the result of the D/A conversion of the digital output in the current stage of circuit 103, 104, or 105.
Consequently, even if the number of converted bits increases to reduce the LSB (Least Significant Bit), the resolution of each of comparators constituting the sub-A/D converter 109 can be substantially improved, thereby obtaining sufficient conversion accuracy.
FIG. 36 is a circuit diagram showing one example of the differential amplifier 114 shown in FIG. 35. FIG. 37 is a diagram for explaining the operations of the differential amplifier circuit 114 shown in FIG. 36.
In FIG. 36, an inverse input terminal of the operational amplifier 111 is connected to a node nb, and a non-inverse input terminal is grounded. An output terminal of the operational amplifier 111 is connected to a node no, and is also connected to the inverse input terminal through a capacitor 102. A switch SW1 is connected between the inverse input terminal and the non-inverse input terminal, and a capacitor 103 is connected between the node nb and a node na. The node na is connected to a node n1 through a SW2, and is also connected to a node n2 through a switch SW3. A voltage V1 is inputted to the node n1, a voltage V2 is inputted to the node n2, a voltage V0 is outputted from the node no.
Referring now to FIG. 37, the operations of the differential amplifier circuit 114 shown in FIG. 36 will be described. Let C be a capacitance value of the capacitor 102, KC be a capacitance value of the capacitor 103, and VG be a ground potential. K is a constant.
First, as shown in FIG. 37, the switch SW1 and the switch SW2 are turned on, and the switch SW3 is turned off. Consequently, the voltage at the node na is V1. Furthermore, the voltage at the node no is 0. At the time, the charge Qa at the node nb is expressed by the following equation:Qa=(VG−V1)KC  (1)
Secondly, as shown in FIG. 37, the switch SW1 is turned off, and then the switch SW2 is turned off and the switch SW3 is turned on. Consequently, the voltage at the node na is V2, and the voltage at the node no is V0. At this time, the node nb is virtually grounded. Therefore, the charge Qb at the node nb is expressed by the following equation:Qb=(VG−V2)KC+(VG−V0)C  (2)
Since there is no path through which charge flows out at the node nb, Qa=Qb from the principle of conservation of charge. Consequently, the following equation holds:(VG−V1)KC=(VG−V2)KC+(VG−V0)C  (3)
From the foregoing equation, the voltage V0 at the node no is expressed by the following equation:V0=VG+(V1−V2)K  (4)
In this manner, the voltage V2 is subtracted from the voltage V1, and the subtracted value is amplified by a factor of K.
These are, however, ideal operations of the differential amplification circuit 114. In reality, an error may occurs in the ratio of accuracy of the capacitance due to manufacturing variations in the differential amplifier circuit 114. Let (K-err) C be the capacitance value of the capacitor 103, and the voltage V0 at the node no by the equation (4) is expressed by the following equation:                                                         VO              =                            ⁢                              VG                +                                                      (                                          V1                      -                      V2                                        )                                    ·                                      (                                          K                      -                      err                                        )                                                                                                                          =                            ⁢                              VG                +                                                      (                                          V1                      -                      V2                                        )                                    ⁢                  K                                -                                                      (                                          V1                      -                      V2                                        )                                    ⁢                  err                                                                                        (        5        )            
where the third item at the right side of the equation (5) represents the gain error of the differential amplification circuit 114 caused by the error in the ratio of accuracy of the capacitance, and err represents the gradient of the gain error.
FIG. 38 is a diagram showing the input/output characteristics of the analog-to-digital conversion circuit 101 shown in FIG. 35. FIG. 39 is an enlarged view of a part of the input/output characteristics shown in FIG. 38. In FIGS. 38 and 39, the abscissa shows the analog input signal Vin, and the ordinate shows the digital output value Dout.
In FIG. 38, the broken line Tr shows the ideal input/output characteristics of the analog-to-digital conversion circuit 101, and the solid line Er shows the input/output characteristics in a case where the differential amplifiers 114 of the analog-to-digital conversion circuit 101 have gain errors.
Ideally, it is desired that the digital output value Dout has a constant proportional relationship with the analog input signal Vin, as shown by the broken line Tr. In a case where the differential amplifier circuits 114 have gain errors, however, a non-linearity error (hereinafter referred to as an interstage gain error) occurs in the input/output characteristics of the analog-to-digital conversion circuit 101, as shown by the solid line Er.
In the analog-to-digital conversion circuit 101 shown in FIG. 35, the gain error of the differential amplifier circuit 114 in the first-stage circuit 103, the gain error of the differential amplifier circuit 114 in the second-stage circuit 104, and the gain error of the differential amplifier circuit 114 in the third-stage circuit 105 impact the input/output characteristics. Since the first-stage circuit 103 outputs the high order 4-bit digital signal D9 to D6, the gain error of the differential amplification circuit 114 in the first-stage circuit 103 impacts the input/output characteristics the most.
Accordingly, by correcting the interstage gain error due to the gain error of the differential amplification circuit 114 in the first-stage circuit, it is possible to reduce the interstage gain error in the input/output characteristics of the analog-to-digital conversion circuit 101.
Gain error components in the input/output characteristics can be found from the digital output value Dout and the gradient err of the gain error in the analog-to-digital conversion circuit 101 before correction. It is thus possible to reduce the interstage gain error by correcting these gain error components by way of digital operations as shown below.
A circuit correcting an error based on an error signal err (D) will be then described.
FIG. 40 is a block diagram showing one example of the structure of the output circuit 108 shown in FIG. 35.
As shown in FIG. 40, the output circuit 108 includes a multiplier 501 and a digital calibration operation unit 502. The digital calibration operation unit 502 is composed of a 10-bit adder.
To the output circuit 108, the digital signals outputted from the first- to fourth-stage circuits 103 to 106 shown in FIG. 35 are inputted. Here, the interstage gain error is corrected using the digital signal D5, D4, which is impacted by the gain error of the differential amplifier circuit 114 in the first-stage.
The digital signals D9 to D0 outputted from the first-to fourth-stage circuits 103 to 106 are supplied to the digital calibration operation unit 502. Of the digital signals D9 to D0, the digital signal D5, D4 outputted from the second-stage circuit 104 is supplied to the multiplier 501.
Furthermore, the error signal err (D) representing the digital value corresponding to the gradient err of the gain error of the differential amplifier circuit 114 in the first-stage is supplied to the multiplier 501. This error signal err is predetermined. The multiplier 501 multiplies the error signal err (D) and the digital signal D5, D4, and supplies the result of multiplication to the digital calibration operation unit 502 as a correction value. The digital calibration operation circuit 502 adds the correction value to the digital signals D9 to D0, and outputs a resulting value as a digital output value Dout.
FIG. 41 is a diagram showing one example of the correction of the interstage gain errors in the output circuit 108 shown in FIG. 40. In FIG. 41, the solid line Tr shows the ideal input/output characteristics, the broken line Er shows the input/output characteristics of the analog-to-digital circuit 101 in a case where the differential amplifier circuits 114 have gain errors, and the solid line Ta shows the input/output characteristics after correction.
In the example of FIG. 41, the maximum value of the interstage gain error in the input/output characteristics is 4LSB. In this case, the error signal err (D) is set to 1LSB. In a case where the digital signal D5, D4 is “0, 0”, the correction value is set to “00” (=0), in a case where “0, 1”, the correction value is set to “01” (=1), in a case where “1, 0”, the correction value is set to “10” (=2), and in a case where “1, 1”, the correction value is set to “11” (=3). By adding this correction value to the values of the 10-bit digital signals D9 to D0, the maximum value of the error in the input/output characteristics after correction to the ideal input/output characteristics is reduced to 1 LSB.
FIG. 42 is a diagram showing another example of the correction of the interstage gain error in the output circuit 108 shown in FIG. 40. In FIG. 42, the solid line Tr shows the ideal input/output characteristics of the analog-to-digital conversion circuit 101, the broken line Er shows the input/output characteristics in a case where the differential amplifier circuits 114 have gain errors, and the solid line Ta shows the input/output characteristics after correction.
In the example of FIG. 42, the maximum value of the interstage gain error in the input/output characteristics is set to 2LSB. In this case, the error signal err (D) is set to 1 LSB. In a case where the digital signal D5, D4 is “0, 0”, the correction value is “00” (=0), in a case where “0, 1”, the correction value is “01” (=1), in a case where “1, 0”, the correction value is “10” (=2), and in a case where “1, 1”, the correction value is “11” (=3). By adding this correction value to the values of the 10-bit digital signal D9 to D0, the maximum value of the error in the input/output characteristics after correction to the ideal input/output characteristics is reduced to 1.5 LSB.
In this manner, the interstage gain error in the input/output characteristics of the analog-to-digital conversion circuit 101 due to the gain errors of the differential amplifier circuits 114 can be reduced.
However, the output circuit 108 in the conventional analog-to-digital conversion circuit 101 includes a multiplier 501. Therefore, its circuit scale is increased.
Furthermore, since the correction value is calculated using the multiplier 501, the correction value is limited to the combination of 0×err (D), 1×err (D), 2×err (D), and 3×err (D). As described in the foregoing, in a case where the correction signal err (D) is set to the minimum value of 1LSB, the correction value is limited to the combination of 0 LSB, 1 LSB, 2 LSB, and 3 LSB. Thus, it is difficult to sufficiently reduce the interstage gain error in the input/output characteristics of the analog-to-digital conversion circuit 101 due to the gain errors of the differential amplifier circuits 114.